1. Field of the Invention
The present invention generally relates to inter-layer insulating materials for multilevel metal interconnection in microelectronics and, more particularly, to a dual-damascene process for patterning vias and trenches within an insulating layer for electrically isolating metal wires on microelectronic chips without etching out the insulating layer.
2. Description of the Related Art
The present invention is directed to a fabrication process for producing via holes and wiring trenches in the inter-layer insulating materials for multilevel metal interconnection microelectronics. For the sake of manufacturing simplicity, it is advantageous to form both the vias and trenches by a single process step. This single process step is ref erred to a "dual-damascene" process. The inter-layer insulator may be silicon dioxide as is currently being used in copper interconnection technology, or a low-k (k=dielectric constant) insulating material as is currently being pursued for the next generation of copper interconnection technology. The present invention is particularly well suited for future interconnection technologies which will demand a minimum feature size much smaller than the present (i.e., feature sizes of below 250 nm).
Current copper-based interconnection technology is based on the dual-damascene process, in which (i) the shape of contact holes and wiring trenches is first formed in an insulating film by reactive ion etching (RIE), (ii) a copper film is next deposited on the insulator, and then (iii) unwanted portion of the copper film is removed by a chemical-mechanical polishing, leaving Cu inside vias and trenches. This invention is primarily directed to the first step of patterning vias and trenches within an insulating layer which electrically isolates between metal wires on microelectronics chips.
There are a number of different fabrication schemes to realize a dual-damascene structure in silicon dioxide film, but each of the prior art methods create major technological difficulties which hampers practical manufacturing applications, particularly when utilizing a low-k insulating material of a poor etch resistance over a photo-resist mask. Prior art dual-damascene processes are discussed below with reference to FIGS. 1 to 5. For simplicity, like structures are given the same reference numerals.
Referring to FIGS. 1a-1d, there is shown a "trench first" dual-damascene process where a long trench pattern is etched first and then via patterns are etched at the bottom of a trench. Specifically, FIG. 1a shows an etch stop layer (ESL) 12 covering Cu wires 10. An insulation layer 14 is deposited over the etch stop layer 12 and a trench pattern 18 is defined in the insulation layer 14 by a photo-resist mask (PR) 16. In FIG. 1b the trench is etched and in FIG. 1c a photo resist mask 20 is deposited in the trench to define the via pattern. Finally, in FIG. 1d, the vias 22 and the etch stop layer 12 are etched with a reactive ion etch (RIE) exposing the wires 10 and the photo-resist masks 16 and 20 are stripped.
The major difficulty of this process sequence is the accuracy of the lithography overlay between the trench pattern and the via hole pattern inside a trench structure. A small misalignment could cause a large decrease in the Cu wire contact area 10, critical for the electrical performance. A pattern definition inside a narrow trench of below sub-250 nm will not be trivial in the future. Other practical issues may arise from the RIE process in terms of an effective etch stop at the bottom of a trench and via hole.
FIGS. 2a-2e shows a schematic of another process sequence called "via-first", where the via holes 22 are etched first and then the trench 18 is etched afterward. Note that the resultant structure shown in FIG. 2e is the same as in the "trench first" process shown in FIG. 1d. In the "via first" case, a resist residue 16 may be left inside via holes 22 during the step of a trench pattern definition and must be cleaned prior to a copper deposition. Unfortunately, just as in the "trench first" case of FIG. 1, the "via first" case of FIG. 2 has the same photo-resist mask overlay alignment problem.
FIGS. 3a-3e describe another dual-damascene process that introduces an additional etch stop layer 24 to overcome the difficulty of stopping at the bottom of vias and trenches. As shown in FIG. 3a, the additional inter-etch stop layer (ESL) 24 is placed on top of the insulation layer 14. Thereafter, a second insulation layer 26 is placed atop of the inter-ESL 24. As shown in FIG. 3b, a photo-resist (PR) mask 28 defines the via pattern 22 over the second insulation layer 26. In FIG. 3c the vias 22 are etched and the inter-ESL 24 is opened with a RIE. In FIG. 3d the trench 18 is patterned and in FIG. 3e the trench 18 and the remainder of the vias 22 are etched with a RIE exposing the wires 10.
A choice of the etch stop layer material, 12 and 24, is limited to a few insulating films compatible to SiO.sub.2 or a low-k insulator 1&lt;k&lt;4. The most popular etch stopper is Si.sub.3 N.sub.4 film. A significant drawback of the nitride film is its high k-value near k=7, in comparison to k=4 for SiO.sub.2 and k=1-3 for a variety of low-k materials. Therefore, the etch stop layer must be very thin to maintain the overall "effective" dielectric constant very low. A higher k-value means a larger RC time constant. The etch stop layer material should have a high etch selectivity over the inter layer insulator for a given RIE process. The actual process flow described in FIG. 3 is similar to the "trench-first" process described in FIG. 1, except for an additional layer of the inter-ESL 24 to ensure the integrity of a physical dimension of vias, 22, and trenches 18.
FIG. 4 shows a similar process sequence as the "via first" process shown in FIG. 2, but with an inter etch stop layer 24 to provide more accurate control of the trench depth 18. After etching vias and stopping at the inter etch stopper 24 (FIGS. 4a-4c), an extra etch step is used to open via mask on the inter etch stop layer 24 as shown in FIG. 4d. Trenches were then patterned with resist masks 26. The trenches 18 and second half of vias 22 are etched at the same time. The trench thicknesses are predetermined by the inter etch stop layer as shown in FIG. 4d.
FIGS. 5a-5d describes yet another dual-damascene process, where two etch steps for vias and trenches are reduced to one etch step. As shown in FIGS. 5a-5b, after the first insulator layer 14 is deposited or spun on the first ESL 12 and the inter etch stop layer 24 is formed, via holes 22 are patterned using a photo-resist mask 16 and opened on the inter-ESL 24. In FIG. 5c, the second insulating layer 26 with a thickness of trench depth 18 is then formed on top of the inter etch stop layer 24. If a trench resist mask 28 is patterned with accurate alignment with the via openings 22 on the inter etch stop layer 24, the trench 18 and vias 22 will be etched in one step. The trenches 18 stop at the inter etch stop layer 24 and vias 22 stop at the second etch stop layer.
The dual-damascene processes described in FIGS. 3, 4, and 5 can only provide a way to accurately control the trench thickness and stopping vias by introducing etch stop layers at the expense of increasing "effective" dielectric constant k value. All other process and integration issues, such as etching via through a deep resist mask, contact area to underlying metal layer, mask alignment accuracy, etc. still remain to be solved. An additional layer of the etch stopper further complicates the dual-damascene process, and an increase in the "effective" k-value significantly limits these process schemes to be viable for future copper interconnection technologies with a low-k insulating material.